It is well known that compressive stress enhances the performance of PMOS transistors and tensile stress enhances the performance of NMOS transistors. Consequently, PMOS transistors with SiGe stress enhancement source and drain regions and NMOS transistors with SiC stress enhancement source and drain regions have been developed. A recess is etched into the silicon in the source and drain regions and the recess is then refilled with epitaxially grown SiGe in for PMOS transistors or SiC for NMOS transistors. Although this process improves transistor performance it also introduces defects that give rise to higher transistor off state leakage and also causes higher electric fields in the channel region that exacerbates channel hot carrier generation degrading transistor reliability. It is therefore desirable to develop a process that takes advantage of the transistor improvement with stress enhancement while significantly reducing the detrimental effects.
When stress enhancement is used in drain extended MOS (DeMOS) transistors, it lowers the sheet resistance of the drain extension. A DeMOS transistor with stress enhanced source and drains therefore requires more area to achieve the equivalent resistance of a DeMOS transistor without stress enhancement. It is desirable to develop a process for DeMOS transistors that benefits from stress enhancement and has the same area as a DeMOS without stress enhancement.